How i3C Works and Its Applications
The use of sensors in mobile devices has grown it is becoming complex for manufacturers to utilize existing methods like i2C & SPI. So, the MIPI alliance members launched the first i3C protocol which is also called (Improved Inter-Integrated Circuits) in the year 2017 by the MIPI Alliance called MIPI I3C v1.0. In October 2018, the MIPI i3C Basic v1.0 was launched, and after that MIPI i3C v1.1 version was released in the month of December 2019. This is an evolution of i2C but both the i2C and i3C include SDA & SCL lines however, the i2C protocol only supports four-speed modes like 100KHz, 400KHz, 1MHz, and 3MHz) whereas I3C supports speeds up to 12.5MHz within single data rate mode. The throughput bit rate of the I3C protocol is high up to12.5Mbps. So this provides brief information on the I3C protocol and its applications.
What is MIPI i3C?
The MIPI i3C Bus interface is an evolutionary specification that builds upon the legacy i2C standard. The aim is to reduce the number of physical pins used in sensor system integration and supports low-power, high-speed digital communication typically associated with UART and SPI interfaces, so that i3C becomes a single interface combining all the capabilities of the legacy interfaces.
The i3C / iIII3 Protocol
The i3C is a MIPI standard protocol that is mainly designed to dominate the limitations of i2C protocol like external signals required for interrupts, limited speed, and no automatic device detection which is connected to the bus. The main function of MIPI is to regulate sensor communication, decrease the number of physical pins utilized within the integration of a sensor system, and support some features like high speed and low power which are presently not covered through SPI & i2C. The MIPI i3C Basic specification states that i3C has significant energy consumption and bus speed improvements over i2C.
The Basic of i3C Serial Bus Protocol
I3C Protocol’s Main Features
• Backward compatibility with legacy I2C
• Multi-Master and Multi-drop capabilities
• Dynamic Addressing
• In-Band Interrupts
• Hot-Join support
Operating an i3C Protocol
The MIPI I3C Bus interface is very helpful in decreasing the number of physical pins utilized within the sensor system & supports high-speed and low-power digital communication which is associated through SPI & UART interfaces so that the I3C protocol will become a single interface to combine different legacy interfaces.
This type of Protocol includes a multi-drop bus at 12.5 MHz and it is 12 times faster as compared to I2C. So, the I3C Protocol interface plays a key role in streamlining sensor integration within smartphones, wearable & IoT devices.
The communication of the I3C protocol can be done in a frame where the frame starts with a START, followed by a minimum of one or above transfers & a STOP. The specification of MIPI i3c will ensure that the format of the CCC command simply follows the rules of SDR protocol. Commands can be addressed to the following:
On the i3C bus, all the devices will use the CCC (Common Command Code) broadcast command like START, 0x7A, CCC command code, additional data, repeated START or STOP; the i3C interface supports SDR (Single Data Rate) and HDR (high data rate) messages. The data transfer at a high data rate is equivalent to CLK cycles. There are two kinds of messages Broadcast & Direct CCC which permits the master to commune with a specific or all slaves on the bus. This protocol mainly depends on the frame encapsulation approach. This frame always includes START, the Header, the data & the STOP. This bus is always initialized within SDR mode & not at all within HDR modes. CCC commands protocol is formatted by using only SDR and CCC is transmitted to specific to slaves or all slaves in the i3C bus.
For the HDR modes:
• First the dedicated Broadcast I3C address(7’h7E) is issued to all slaves on the I3C bus.
• Then one of the Enter HDR CCC’s is issued, indicating that the Master is entering the HDR mode. Each HDR mode has its own Enter HDR CCC.
• This is followed by one or more HDR transfers.
• HDR mode is ended by using the HDR exit pattern protocol.
For more details on I3C protocols, please refer to MIPI® I3C specifications.
I3C devices have Bus and Device characteristic registers which will hold information about the capabilities of I3C device.
I3C bus can be configured with multiple devices. These devices are I3C Main Master, I3C secondary Master, I3C Slave and I2C Slave.
Where i3C Protocol can be implemented or used?
i3C protocol is used as a standard for integrating sensors in the System. Temperature sensors, gyroscopes, etc. There are new interesting applications for i3C interfaces in data centers as management buses. i3C Protocol Message Format i3C protocol uses a 2-wire bidirectional serial bus, which includes the SDA data line & SCL clock line. In SDR mode, the data transfer can be done up to 12.5Mbps including 12.5 MHz CLK frequency. The transaction of the i3C bus starts with the START condition. Here, SCL must be held high & SDA must go from high to low, following that the slave device address or broadcasted address through R/W bit must be sent.
After the first start address, arbitration may occur within the I3C bus, the device with a small address value would win. For the broadcast address, all the slave devices over the I3C bus must send acknowledgment apart from I2C slaves. For slave addresses, simply a particular slave transmits acknowledgment. Once the ACK, i3C bus continues with write, and read otherwise CCC command data is transferred then the i3C master can decide to STOP. Here, SCL should be held high & SDA must go from low to high otherwise can provide a repeated start after a transaction with the host controller command.
ACK – Acknowledge (SDA Low).
NACK – Not Acknowledge.
S – Start Condition.
Sr – Repeated Start Condition.
P- Stop Condition.
T – Transition bit Alternative to ACK or NACK.
PAR – Parity Bit.
i3C VS i2C PROTOCOL
The comparison between the i3C and i2C protocols is the following.