SPI-Communication-DiagramThe SPI(Serial to Peripheral Interface) develop by Motorola and later adopted by Microwire of National Semiconductor and other companies. SPI is a hardware / firmware communication protocol or sometimes Engineers called it a “four wire serial bus” communication.

The SPI Bus is a 4 wire serial communication interface used by many microprocessors and micro controller chip to enables the controllers and peripheral devices to communicate the two devices. Even it is develop primarily for the communication between Server/Host processor and peripherals, a connection of two processor via SPI it will go well smoothly. This SPI Bus its operates at full duplex meaning, signal carrying data can go back and forth in any direction simultaneously, a synchronous type of data setup MASTER / SLAVE interface, SPI also support up to 1 magaboud or 10Mbps of speed. SPI can adopt single-master and multi-master protocols but the multi-master bus is rarely used, and are usually limited to a single slave.
The SPI Bus is usually used only on the PCB and there are many facts which prevent us from using it outside the PCB Board. Actually the SPI Bus is designed to transfer data between various IC chips, at very high speeds, Due to this high-speed, the bus lines cannot be to long, because their reactance increases, and the Bus become unusable. However, its possible to use the SPI Bus outside the PCB at low speed, but this is not quite advisable.

The peripherals can be a Real Time Clock, converts like ADC and DAC memory module it is like EEPROM and FLASH, temperature sensors, signal-mixer, potentiometer, LCD Controller, UART, CAN controller, USB Controller and amplifier.

The Data and Control lines of the SPI connection:
An SPI Protocol use 4 signal wires.

1. MOSI(Master Out Slave In) – MOSI signal is generated by master recipient is the slave.
2. MISO(Master In Slave Out) – Slave generate MISO signal and recipient is the master
3. SCK/SCLK(Serial Clock) – SCLS/SCK signal is generated by the mater to synchronize data transfer between the master and slave.
4. SS(Slave Select) from master Chip Select(CS) of slave – SS signal is generated by master to select individual slave devices. The SS/CS is an active low signal.

There are other naming conventions such as SDI(Serial Data In) in place of MOSI and SDO(Serial Data Out) for MISO.


These four logic signals, the two of them MOSI(Master Out Salve In) & MISO(Master In Slave Out) can be grouped as data lines and the two SS(Slave Select) & SCLK(Serial Clock) as the control lines.
The SPI(Serial to Peripheral Interface) Bus communication there can be one master with a multiple slaves. In single master protocol, usually one SPI device act as the SPI Master and controls the data flow by generating the clock signal and enabling the slave to be wanted to communicate with slave select signal or SS, then receives and or transmit the data via two lines. A micro controller as a host always provides clock signal to all devices on a bus whether it is selected or not.
The use of these four pins may depend on the devices. For example, SDI pin may not be present if a device does not require an input the ADC for example or SDO pin may not be present if a device does not require an output the LCD controller for example. If a microcontroller only needs to talk to one SPI peripheral or one slave, then the CS pin on that slave may be grounded. Using multiple slave devices, as an independent SS signal is needed from the master for each slave devices.

How Master & Slave communicate?

Communication is initiated always by the master. The master firstly configures the clock, using a frequency, which is less that or equal to the maximum frequency that the slave supports. The master will select the desired slave for the communication by pulling the chip SS(Slave Select) line then making the particular slave peripheral to LOW state, waiting period is needed such as for ANALOG to DIGITAL conversion then the master must wait for at least a period of time before starting to provide clock cycle.


The slaves on the bus has not been activated by the master using SS(Slave Select) signal will disregard the input clock and MOSI signal from the master and should not be drive by MISO(Master In Slave Out) it means that the master select only one slave at a time.

Most peripherals/devices have tri-state output, which goes to high impedance state it will disconnected when the device/peripherals is not selected. Devices without this tri-state output cannot share the SPI(Serial to Peripheral Interface) Bus along with other devices, because the slave chip-select may not get enabled.

The Full Duplex Transmission can occur during each clock cycle, the master send a bit on the MOSI(Master Out Slave In) line the slave reads it from that same line and the slave sent a bit going to MISO(Master In Slave Out) line and the master will reads at the same line.


The data transfer is prearrange by using SHIFT REGISTER by providing some word size such as 8BITS,but remember both master and slave it is not limited to 8BIT they are connected to ring. While the master shifts register value out though MOSI(Master Out Slave In) line the slave shifts the data into its SHIFT REGISTER.

The data are usually shifted first out with the MSB(MSB in an 8-bit binary number represents a value of 128 decimal) while shifting a new LSB(Least Significant Bit represents a value of 1) into the same register. When the register has been shift out the master and slave should exchanged their register value. Each device takes the value and it will operates on it, like for example writing into the memory, if there are more data to exchanged the shift registers will be loaded with new data and it will process repeatedly, then if there is no data to be transmitted, the master clock will stop automatically then rejects the slave.

There is a MULTIPLE BYTE STREAM mode in SPI Bus interface. one is the master can shift bytes continuously the SS(Slave Select) is keep LOW until all stream process will get finished, The SPI devices sometimes used another signal to send interrupt signal to the host CPU. some of this example are Pen-Down interrupts from the Touch Screen Sensors, Thermal limit notification from temperature sensor, alarms issued by Time Clock Chip and the header jack insertions from the sound codec in a cell phone.

The Clock polarity and Phase

Another SPI parameters called CPO(Clock Polarity) and CPHA(Clock Phase) this parameters can determine the edges of the clock signal on which the data are driven and sampled. Adding up to the setting to the clock frequency, the master should also configure the CPO(Clock Polarity) and CPHA(Clock Phase) along with the data. Since the clock is synchronize the data communication, there are four modes can be used in the SPI Protocol. base on Clock Polarity and Clock Phase.


If the segment of the clock phase is zero the data is latched at the rising edge of the clock along with clock polarity zero and at the falling edge of the clock polarity it becomes 1. then if clock phase is one the polarities are reversed. Data is latched at the falling edge of the clock along with clock polarity zero, and at the rising edge of clock polarity equal to one.

The microcontroller allow the polarity and the clock phase to be adjusted, positive polarity results in latching the data at the rising edge of the clock. However the data is on the line already at the falling edge to stabilize most devices and peripherals which can be slave and works on this configuration, and it should become necessary to use the other polarity if transitions are reversed.

The SPI Peripherals different types of configurations:

If the master microcontroller needs to converse to a multiple SPI Peripherals there will be two methods to do this setup.

  1. Daisy Chained / Cascaded Slaves
  2. Parallel Configuration / Independent Slaves

The Daisy Chained Configuration Diagram

As you can see in Cascaded Slave Configuration all the SCLK (Serial Clock) line are connected together, and also all the CS (Chip Select) pins are connected, the data transmission out to the microcontroller through each peripheral and data flow will go back to forth to microcontroller. The data output of previous slave device is tied to data input of the next forming a wider shift register. so that cascaded slave devices are evidently looked at as one larger device and receive therefore the same CS chip signal. it means only the single SS line is required from the master rather than a separate SS line on each slave.


Note: you have to remember that the Daisy Chain will not work with devices that requires multiple bytes operation.

The Independent slave configuration diagram

This diagram has a typical SPI Bus configuration with one SPI master and multiple slave devices/peripheral. As you can see on the diagram all SCLK clock lines are connected together, MISO data lines are all connected together, MOSI data lines are connected together but the CS pin from each devices/peripheral must be connected to a separate SS (Slave Select) pin on the master controller.


The QSPI (Queued Serial Peripheral Interface)

The QSPI is a controller extension for the SPI Bus. The difference is that it uses a data queue with programmable queue pointers that allow the data transfers without the CPU intervention it also has a wrap-around mode that allows continuous transfers and from the queue with no CPU intervention. The result will the peripherals appear to the CPU as memory-mapped parallel devices. this is useful in application such as controlling the Analog to Digital converter and the QSPI has some more programmable features like chip select and transfer length delay.

What is the difference of SPI & QSPI?

SPI (Serial Peripheral Interface) – Requires CPU Intervention
QSPI (Queued Serial Peripheral Interface) – Does not require CPU Intervention

What the advantage of SPI(Serial Peripheral Interface)?

  • SPI has a full duplex communication
  • SPI has a higher throughput than I2C protocol
  • SPI ha a simple hardware interfacing
  • It has a lower power requirements than I2C due to less circuitry.
  • It is not limited to 8-bit words in the case of bit-transferring
  • It has arbitrary choice of message size, contents, and purpose
  • No arbitration or associated failure modes.
  • Slaves use the master’s clock, and don’t need precision oscillators.
  • Transceivers are not needed.
  • At most one “unique” bus signal per device CS; all others are shared

What is the disadvantages of SPI(Serial Peripheral Interface)?

  • It’s requires more pins on IC packages than I2C.
  • No in-band addressing. Out-of-band chip select signals are required on shared busses.
  • No hardware flow control.
  • No slave acknowledgment.
  • It has a multi-master busses are rare and awkward, and are usually limited to a single slave.
  • without a formal standard, validating conformance is not possible.
  • Only handles short distances compared to RS232, RS485, or CAN.
How SPI, QSPI Serial to Peripheral Interface Woks ?
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One thought on “How SPI, QSPI Serial to Peripheral Interface Woks ?

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    The SS arrow in the first graphic is in the wrong direction. The SPI master SS signal is an output to the SPI slave.


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